Design and implementaion of a 2D-DCT architecture using coefficient distributed arithmetic [implementaion read implementation]
作者： S. Ghosh , S. Venigalla , M. Bayoumi
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摘要: The paper describes the design and implementation of an 8 /spl times/8 2D DCT chip for use in low-power applications. exploits a coefficient distributed arithmetic (CoDA) scheme as opposed to prevalent data (DDA) schemes achieve low power consumption. architecture uses no ROMs minimum number additions by exploiting redundancy adder arrays. described CoDA is implemented on FPGA has been fabricated silicon. computes @ 50 MHz consuming around 137mW power.
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acm.org 参考文章(9)
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