作者: Y.-H. Chan , W.-C. Siu
DOI: 10.1109/81.250161
关键词: Arithmetic 、 Realization (systems) 、 Chip 、 Very-large-scale integration 、 Prime (order theory) 、 CMOS 、 Mathematics 、 Convolution 、 Overhead (computing) 、 Discrete cosine transform
摘要: A unified approach to the realization of forward and inverse discrete cosine transforms is proposed. With this approach, an odd prime length DCT/IDCT with two half-length convolutions can be realized without extra overhead in terms number multiplications. The formulation most suitable for using distributed arithmetic, which case typical convolvers used as core unit hardware implementation transforms. Hence, efficient chip proposed demonstrate superiority formulation. architecture easily meet speed requirement 14.3 MHz real-time operation current 2 mu m CMOS technology. >