A Self-Reconfigurable Platform for Scalable DCT Computation Using Compressed Partial Bitstreams and BlockRAM Prefetching
作者： Jian Huang , Jooheung Lee , None
DOI: 10.1109/TCSVT.2009.2031464
关键词: Circuit design 、 Auxiliary memory 、 Scalability 、 Control reconfiguration 、 Parallel computing 、 Cache 、 Discrete cosine transform 、 Field-programmable gate array 、 CPU cache 、 Integrated circuit 、 Computer science 、 Data compression 、 Application-specific integrated circuit
摘要: In this paper, we propose a self-reconfigurable platform which can reconfigure the architecture of discrete cosine transform (DCT) computations during run-time using dynamic partial reconfiguration. The scalable DCT compute different numbers coefficients in zig-zag scan order to adapt requirements, such as power consumption, hardware resources, and performance. We configuration manager, is implemented embedded processor adaptively control reconfiguration run-time. addition, use Lempel-Ziv-Storer-Szymanski algorithm for compression bitstreams on-chip BlockRAM cache reduce latency overhead loading from off-chip memory A module designed parallel bitstreams. experimental results show that our approach external accesses by 69% achieve 400 MB/s rate. Detailed trade-offs power, throughput, quality are investigated, used criterion self-reconfiguration.
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