A new framework to accelerate Virtex-II Pro dynamic partial self-reconfiguration

摘要: The Xilinx Virtex family of FPGAs provides the ability to perform partial run-time reconfiguration, also known as dynamic reconfiguration (DPR). Taking this concept one step further, self-reconfiguration becomes possible through internal configuration access port (ICAP). In paper a framework for lowering times using combitgen tool reduce overhead found within bitstreams, along with completely new, very simple and area efficient ICAP controller that is connected directly processor local bus (PLB) equipped direct memory (DMA) capabilities presented. Using PLB Master controller, it reach maximum practical throughput can be achieved interface Virtex-II Pro devices. Compared an alternative realization OPBHWICAP provided by (a slave attachment on on-chip peripheral bus), achieve improvements concerning factor 20.