Realtime configuration code decompression for dynamic FPGA self reconfiguration: evaluation and implementation

摘要: Xilinx Virtex FPGAs have the possibility of dynamical partial runtime reconfiguration. If a system uses this feature with many different configuration bitstreams for substitution parts in reconfiguration memory, amount neccesary memory increases. The sum amounts which to be provided data is not negligible. This fact suggests investigation compressing before they are stored modules system. compressed bitstream has decrompressed transferring it FPGA. paper shows an approach at design time and decompressing them hardware module implemented on FPGA while runtime.