A low-power DCT core using adaptive bitwidth and arithmetic activity exploiting signal correlations and quantization
作者： T. Xanthopoulos , A.P. Chandrakasan
DOI: 10.1109/4.841502
关键词:
摘要: This work describes the implementation of a discrete cosine transform (DCT) core compression system targetted to low-power video (MPEG2 MP@ML) and still-image (JPEG) applications. It exhibits two innovative techniques for arithmetic operation reduction in DCT computation context along with standard voltage scaling such as pipelining parallelism. The first method dynamically minimizes bitwidth operations presence data spatial correlation. second trades off power dissipation image quality (arithmetic precision). chip dissipates 4.38 mW at 14 MHz 1.56 V.
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sci-hub.se 参考文章(16)
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