VLSI implementation of a 16*16 discrete cosine transform
作者： M.-T. Sun , T.-C. Chen , A.M. Gottlieb
DOI: 10.1109/31.92893
关键词:
摘要: The implementation of a 16*16 discrete cosine transform (DCT) chip using concurrent architecture is presented. contains 32 processing elements working in parallel and random-access memory (RAM) which performs matrix transposition. structure highly regular modular, thus very efficient for VLSI implementation. was designed real-time 14.3-MHz sample video data. It an equivalent half billion multiplications accumulations per second. Fabricated 2- mu m double-metal CMOS technology, the approximately 73000 transistors occupy 7.2*7.0-mm/sup 2/ area. 68-pad die size 8.3*8.1 mm/sup 2/. fully functional first DCT chip. accuracy studies finite-wordlength are circuit design layout symbolic tool MULGA described detail. Possible variations also discussed multipurpose (variable sizes, forward-inverse transform) applications. >
sci-hub.se 参考文章(12)
M. T. Sun, T. C. Chen, A. Gottlieb, L. Wu, M. L. Liou, A 16X16 Discrete Cosine Transform Chip visual communications and image processing. ,vol. 0845, pp. 13- 19 ,(1987) , 10.1117/12.976479
N. Ahmed, T. Natarajan, K.R. Rao, Discrete Cosine Transform IEEE Transactions on Computers. ,vol. 23, pp. 90- 93 ,(1974) , 10.1109/T-C.1974.223784
F. Jutand, N. Demassieux, M. Dana, J-P . Durandeau, G. Concordel, A. Artieri, E. Mackowiack, L. Bergher, A 13.5 MHz Single Chip Multiformat Discrete Cosine Transform visual communications and image processing. ,vol. 0845, pp. 6- 13 ,(1987) , 10.1117/12.976478
B. Sikström, L. Wanhammar, M. Afghahi, J. Pencz, A high speed 2-D discrete cosine transform chip Integration. ,vol. 5, pp. 159- 169 ,(1987) , 10.1016/0167-9260(87)90007-1
N. H. E. Weste, MULGA-An Interactive Symbolic Layout System for the Design of Integrated Circuits Bell System Technical Journal. ,vol. 60, pp. 823- 857 ,(1981) , 10.1002/J.1538-7305.1981.TB03383.X
M. Vetterli, A. Ligtenberg, A Discrete Fourier-Cosine Transform Chip IEEE Journal on Selected Areas in Communications. ,vol. 4, pp. 49- 61 ,(1986) , 10.1109/JSAC.1986.1146289
Martin Vetterli, member Eurasip, Henri J. Nussbaumer, Simple FFT and DCT algorithms with reduced number of operations Signal Processing. ,vol. 6, pp. 267- 278 ,(1984) , 10.1016/0165-1684(84)90059-8
Bryan Ackland, Neil Weste, FUNCTIONAL VERIFICATION IN AN INTERACTIVE SYMBOLIC IC DESIGN ENVIRONMENT California Institute of Technology. ,(1981)
Wen-Hsiung Chen, C. Smith, S. Fralick, A Fast Computational Algorithm for the Discrete Cosine Transform IEEE Transactions on Communications. ,vol. 25, pp. 1004- 1009 ,(1977) , 10.1109/TCOM.1977.1093941
A. Peled, Bede Liu, A new hardware realization of digital filters IEEE Transactions on Acoustics, Speech, and Signal Processing. ,vol. 22, pp. 456- 462 ,(1974) , 10.1109/TASSP.1974.1162619