Parallel 4/spl times/4 2D transform and inverse transform architecture for MPEG-4 AVC/H.264
作者： Tu-Chih Wang , Yu-Wen Huang , Hung-Chi Fang , Liang-Gee Chen
DOI: 10.1109/ISCAS.2003.1206095
关键词: Real-time computing 、 Sub-band coding 、 Hardware architecture 、 Computer hardware 、 Lapped transform 、 MPEG-4 、 Context-adaptive binary arithmetic coding 、 Transform coding 、 Coding tree unit 、 Scalable Video Coding 、 Macroblock 、 Computer science
摘要: Transform coding has been widely used in video standards. In this paper, a hardware architecture for accelerating transform operations MPEG-4 AVC/H.264 is presented. This calculates 4 inputs parallel by fast algorithms described previously. The transpose are implemented register array with directional transfers. mapped into /spl times/ multiple transforms unit and synthesized TSMC 0.35um technology. processor can process 320M pixels/sec at 80Mhz all AVC/ H.264.
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