A low-complexity 2D discrete cosine transform processor for multimedia applications
作者： L. Fanucci , R. Saletti , F. Vavala
DOI: 10.1109/ICECS.1999.812319
关键词:
摘要: This paper describes the project of a processor for calculation direct/inverse two-dimensional discrete cosine transform to be employed in videoconference applications. makes use separability technique as method and an architecture based on distributed arithmetic, which multipliers are replaced by accumulation-and-shift blocks. The was implemented AMS 0.8 /spl mu/m technology with semi-custom approach order realize IP macro-cell integrated multimedia ICs. It features very low-complexity (15 kgates) overall area 33 mm/sup 2/ maximum frequency 36 MHz. Besides, is fully compliant accuracy specifications H.263 recommendation.
sci-hub.se 参考文章(5)
S. Uramoto, Y. Inoue, A. Takabatake, J. Takeda, H. Yamashita, H. Terane, M. Yoshimoto, A 100-MHz 2-D discrete cosine transform core processor IEEE Journal of Solid-state Circuits. ,vol. 27, pp. 492- 499 ,(1992) , 10.1109/4.126536
Wen-Hsiung Chen, C. Smith, S. Fralick, A Fast Computational Algorithm for the Discrete Cosine Transform IEEE Transactions on Communications. ,vol. 25, pp. 1004- 1009 ,(1977) , 10.1109/TCOM.1977.1093941
T. Kuroda, T. Fujita, S. Mita, T. Nagamatsu, S. Yoshioka, K. Suzuki, F. Sano, M. Norishima, M. Murota, M. Kako, M. Kinugawa, M. Kakumu, T. Sakurai, A 0.9-V, 150-MHz, 10-mW, 4 mm/sup 2/, 2-D discrete cosine transform core processor with variable threshold-voltage (VT) scheme international solid-state circuits conference. ,vol. 31, pp. 1770- 1779 ,(1996) , 10.1109/JSSC.1996.542322
M.-T. Sun, T.-C. Chen, A.M. Gottlieb, VLSI implementation of a 16*16 discrete cosine transform IEEE Transactions on Circuits and Systems. ,vol. 36, pp. 610- 617 ,(1989) , 10.1109/31.92893
P. Pirsch, N. Demassieux, W. Gehrke, VLSI architectures for video compression-a survey Proceedings of the IEEE. ,vol. 83, pp. 220- 246 ,(1995) , 10.1109/5.364465