VLSI implementation of two-dimensional DCT processor in real time for video codec

摘要: A new VLSI circuit for computing the two-dimensional discrete cosine transform (2D-DCT) using Philips fast computational algorithm a video codec in real time has been designed and tested 1- mu m CMOS standard cell technology. This processor requires minimum number of arithmetic components satisfies CCITT standards possible bits coefficients internal word length compared to other architectures. The architecture is so flexible that it can be used inverse DCT processing just by changing control signals. works at 32-MHz rate. still picture motion compression. Due its high-speed capability codecs different bit rates. >