Stacked die package for peripheral and center device pad layout device
作者： Roslan Bin Said , Dalson Ye Seng Kim , Chong Chin Hui , Lee Wang Lai
DOI:
关键词: Electrical conductor 、 Semiconductor device 、 Optoelectronics 、 Computer hardware 、 Die (integrated circuit) 、 Materials science 、 Substrate (printing)
摘要: An assembly method is disclosed that includes providing a substrate, securing first semiconductor device on surface thereof, and superimposing at least second partially over the device. outer peripheral portion of overhangs both substrate. Discrete conductive elements are placed between Intermediate portions discrete pass outside side Assemblies packaged devices formed in accordance with also disclosed.
lens.org 参考文章(24)
Marcos Karnezos, Tab grid array ,(1993)
Jeffrey Tuck Fock Toh, Kim Hoch Tey, Min Yu Chan, Chee Kiang Yew, Semiconductor device testing and burn-in methodology ,(1998)
Thomas J. Massingill, Thin cavity down ball grid array package based on wirebond technology ,(1994)
Blaine J. Thurgood, Stress balanced semiconductor packages, method of fabrication and modified mold segment ,(2002)
Setho Sing Fee, Tay Wuu Yean, Lim Thiam Chye, Methods for forming a slot with a laterally recessed area at an end thereof through an interposer or other carrier substrate ,(2003)
Michael B. Ball, Multi-chip stacked devices ,(1993)
Larry D. Kinsman, Bumped die and wire bonded board-on-chip package ,(2004)
Katsuhito Kikuma, Hayato Okuda, Akira Takashima, Yuji Akashi, Takao Nishimura, Kaname Ozawa, Mitsutaka Ikeda, Hiroshi Onodera, Fumihiko Ando, Tadashi Uno, Yoshihiro Tsukidate, Stacked semiconductor device and method of producing the same ,(2001)
Walter L. Moden, Flip-chip adaptor package for bare die ,(2006)
Naoto Kimura, Stacked chip-size package type semiconductor device capable of being decreased in size ,(2002)