Strained isolation regions

作者: Mong-Song Liang , Hao-Ming Lien , Kuo-Tai Huang , Chih-tang Peng , Tze-Liang Lee

DOI:

关键词: TrenchMaterials scienceSubstrate (printing)TransistorDielectricChemical-mechanical planarizationSemiconductor structureStress (mechanics)Ultimate tensile strengthComposite materialElectronic engineering

摘要: An isolation trench having localized stressors is provided. In accordance with embodiments of the present invention, a formed in substrate and partially filled dielectric material. an embodiment, layer planarization step performed to planarize surface substrate. The material then recessed below portion trench, may remain along sidewalls or be removed sidewalls. A stress film, either tensile compressive, over within portion. film also extend transistor other semiconductor structure.

参考文章(23)
Chih-Hsin Ko, Chien-Chao Huang, Chung-Hu Ke, Transistor mobility by adjusting stress in shallow trench isolation ,(2004)
Peter K. Moon, David T. Krick, Berni W. Landau, Shallow trench isolation technique ,(1995)
Thomas Hoffmann, Christopher Auth, Mark Armstrong, M. Shaheed, Increasing stress-enhanced drive current in a MOS transistor ,(2003)
Dureseti Chidambarrao, Omer H. Dokumaci, Embedded stressed nitride liners for CMOS performance improvement ,(2004)
Fu-Liang Yang, Chenming Hu, Wen-Chin Lee, How-Yu Chen, Chien-Chao Huang, Yee-Chia Yeo, Semiconductor-on-insulator chip incorporating strained-channel partially-depleted, fully-depleted, and multiple-gate transistors ,(2003)
Keith E. Witek, Stephen Shiu-Kong Poon, Mike Hsiao-Hui Chen, Capped shallow trench isolation and method of formation ,(1998)
Steven M. Kandetzke, Constance J. Araps, Ellen L. Kutner, Mark A. Takacs, Method for preparation of semiconductor structures and devices which utilize polymeric dielectric materials ,(1984)