A fused hybrid floating-point and fixed-point dot-product for FPGAs

摘要: Dot-products are one of the essential and recurrent building blocks in scientific computing, often take-up a large proportion acceleration circuitry. The dot-products is very well suited for Field Programmable Gate Arrays (FPGAs) since these devices can be configured to employ wide parallelism, deep pipelining exploit highly efficient datapaths. In this paper we present dot-product implementation which operates using hybrid floating-point fixed-point number system. This design receives inputs, generates output. Internally it makes use configurable word-length internal representation tuned match desired accuracy. Results high-end Xilinx FPGA an order 150 demonstrate that, equivalent accuracy metrics, possible utilize 3.8 times fewer resources, operate at 1.62 faster clock frequency, achieve significant reduction latency when compared direct core based dot-product. Combining results utilizing spare resources instantiate more units parallel, overall speed-up least 5 times.