Accurate and efficient layout-to-circuit extraction for high-speed MOS and bipolar/BiCMOS integrated circuits
作者： F. Beeftink , A.J. Van Genderen , N.P. Van Der Meijs
关键词: BiCMOS 、 Parasitic extraction 、 Circuit extraction 、 Electronic engineering 、 Bicmos integrated circuits 、 Computer science 、 Integrated circuit layout 、 Capacitance
摘要: In this paper, we describe how have exploited the advantages of various methods for device recognition and modeling in a layout-to-circuit extractor, called Space. Hence, obtained program that, different technologies, can quickly translate large layout into an equivalent network. The network includes parasitics interconnects directly be simulated by simulation packages, such as Spice. efficiency accuracy extractor are confirmed experimental results enable fast reliable verification both MOS bipolar/BiCMOS technologies.
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