Write back and invalidate mechanism for multiple cache lines
作者： Rodney E Hooker
DOI:
关键词: Cache pollution 、 Parallel computing 、 Cache invalidation 、 Cache 、 Cache coloring 、 Cache algorithms 、 Bus sniffing 、 CPU cache 、 Computer science 、 Write buffer
摘要: A microprocessor apparatus is provided that enables write back and invalidation of a block cache lines from memory. The includes translation logic and execution logic. logic translates a block write invalidate instruction into micro instruction sequence directs to write lines from cache to coupled the translation receives the micro sequence, issues transactions over a memory bus writes data corresponding each of the within block.
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