Cache line replacing system for simultaneously storing data into read and write buffers having multiplexer which controls by counter value for bypassing read buffer

摘要: A cache line replacing apparatus for use in a computer system having central processing unit (CPU), main memory and memory, which information of CPU/cache bus is written-back into the desired read from to transmit bus, including first storage write-back data stored, second register increasing count value thereof when stored means decreasing means, multiplexer selectively transmitting or according register. Accordingly, time delay due buffering can be avoided CPU without loss bandwidth.