Pipelined cache memory deallocation and storeback

摘要: A deallocation pipelining circuit for use in a cache memory subsystem. The is configured to initiate storeback buffer (SBB) transfer of first line data stored array if the detects miss signal corresponding and identifies as modified data. issue request bus interface unit after completion SBB transfer. initiates receiving acknowledge from unit. still further deallocate This occurs regardless status whereby pending fill may proceed prior In one embodiment, includes second segments storing segment respectively. this able detect during preferably an response manner, initiation precedes