Method of fabricating an MOS dynamic RAM with lightly doped drain
作者： Paul J. Tsang , Seiki Ogura
DOI:
关键词: Materials science 、 Electronic engineering 、 Optoelectronics 、 Field oxide 、 Impurity 、 Dynamic random-access memory 、 Reactive-ion etching 、 Ion implantation 、 Insulator (electricity) 、 Electrode 、 Doping
摘要: A method of manufacturing LDD MOS FET RAM capable delineating short (less than 1 micrometer) lightly doped drain regions. An N- implant is effected between gate electrodes and field oxide insulators, before the N+ implant. insulator layer then deposited also prior to ion implantation. Reactive etching leaves narrow dimensioned regions adjacent electrode which serves protect portions impurity region during subsequent These protected are source/drain
lens.org 参考文章(13)
Perry W. Lou, James E. Ponder, Graham S. Tubbs, Three level interconnect process for manufacture of integrated circuit devices ,(1979)
Phillip J. Salsbury, Richard T. Simko, Double polycrystalline silicon gate memory device ,(1974)
Jacob Riseman, Irving T. Ho, Method for forming a narrow dimensioned mask opening on a silicon body utilizing reactive ion etching ,(1978)
Robert H. Dennard, Vincent L. Rideout, Method of fabricating self-aligned contact vias ,(1978)
Ronald Silverman, Andres G. Fortino, Henry J. Geipel, Lawrence G. Heller, Method of making a transistor array ,(1979)
George Elwood Smith, Methods for making transistor structures ,(1976)
Jacob Riseman, Irving T. Ho, Method for forming diffusions having narrow dimensions utilizing reactive ion etching ,(1978)
Marcel Roche, Method of manufacturing field effect transistors of the MOS-type ,(1978)