Method and apparatus for avoiding excessive delay in a pipelined processor during the execution of a microbranch instruction

摘要: In a pipelined instruction execution system including microstore for storing sequences of microinstruction addresses associated with each macroinstruction, nanostore randomly unique microinstructions, and an unit executing the no-op/prefetch apparatus, according to present invention, prevents address, stored in microstore, from accessing forces no-op address into when executes conditional microbranch instruction. A microinstruction, corresponding is retrieved executed unit. During unit, apparatus permits either next sequential following access or another non-sequential nanostore, selection said depending upon outcome by As result, are utilized, only one cycle delay, resolution pipeline, will be encountered branch Furthermore, additional real estate available on integrated circuit chip which disposed.