An Inductive-Coupling Inter-Chip Link for High-Performance and Low-Power 3D System Integration

摘要: Three-dimensional (3D) system integration is one of the promising candidates for next-generation high-performance and low-power LSI systems. In 3D integration, we can implement analog digital circuits in chips their optimal process they are stacked connected through vertical inter-chip link. Development wide-band link key factor to realize integration. One most attractive applications processor-memory interface since memory capacity bandwidth a bottleneck processor system. Integrating large size on increases die (SRAM) or steps (eDRAM), either way, raising cost leakage. It desired consumer electronics that chip each fabricated integrated by heterogeneous stacking package. technical challenges wide between memory. The gap computing power communication be filled if area used data rather than periphery only. A Micro-bump capacitive-coupling (Fazzi et al., 2008) interfaces, but only two placed face-to-face. Through Silicon Via (TSV) (Koyanagi 2009) has fewer limitations, it requires additional production equipment. An inductive-coupling (Miura 2007) as wireless TSV, with small impact cost. circuit solution standard CMOS process, hence less expensive TSV. bears comparison TSV performance. rate 11Gb/s/channel efficiency 65fJ/b (Niitsu 2008). 1Tb/s aggregated achieved arranging 1000 channels 1mm