A 390MHz Single-Chip Application and Dual-Mode Baseband Processor in 90nm Triple-Vt CMOS
作者： Masayuki Ito , Minoru Sakata , Masayuki Yamamoto , Yuji Arai , Toshihiro Hattori
DOI: 10.1109/ISSCC.2007.373400
关键词:
摘要: A single-chip 11.15times11.15mm2 application and dual-mode WCDMA/HSDPA GSM/EDGE baseband processor achieves 390MHz in triple-V, low-power 90nm 8M CMOS. CPU core standby mode with resume cache reduces leakage current of each to 0.04mA when idle. dynamic bus clock-stop scheme further power consumption. Interconnect buffers allow the chip support 30f/s VGA video.
sci-hub.se 参考文章(2)
T. Kamei, M. Ishikawa, T. Hiraoka, T. Irita, M. Abe, Y. Saito, Y. Tawara, H. Ide, M. Furuyama, S. Tamaki, Y. Yasu, Y. Shimazaki, M. Yamaoka, H. Mizuno, N. Irie, O. Nishii, F. Arakawa, K. Hirose, S. Yoshioka, T. Hattori, A resume-standby application processor for 3G cellular phones international solid-state circuits conference. pp. 336- 531 ,(2004) , 10.1109/ISSCC.2004.1332731
T. Hattori, T. lrita, M. Ito, E. Yamamoto, H. Kato, G. Sado, Y. Yamada, K. Nishiyama, H. Yagi, T. Koike, Y. Tsuchihashi, M. Higashida, H. Asano, I. Hayashibara, K. Tatezawa, Y. Shimazaki, N. Morino, K. Hirose, S. Tamaki, S. Yoshioka, R. Tsuchihashi, N. Arai, T. Akiyama, K. Ohno, A Power Management Scheme Controlling 20 Power Domains for a Single-Chip Mobile Processor international solid-state circuits conference. pp. 2210- 2219 ,(2006) , 10.1109/ISSCC.2006.1696282