Pipelined multithreading transformations and support mechanisms

摘要: Even though chip multiprocessors have emerged as the predominant organization for future microprocessors, multiple on-chip cores do not directly result in improved application performance (especially legacy applications, which are predominantly sequential C/C++ codes). Consequently, parallelizing applications to execute on is essential their success. Independent multithreading techniques, like DOALL extraction, create partially or fully independent threads, communicate rarely, if at all. While such strategies keep high inter-thread communication costs from impacting program performance, they cannot be applied parallelize general-purpose characterized by difficult-to-break recurrences. cyclic DOACROSS, more applicable, dependences created these techniques cause them very low tolerance rising inter-core latencies. To address problems, this work introduces a pipelined (PMT) transformation called Decoupled Software Pipelining (DSWP). DSWP, particular, and PMT general, able tolerate latencies, while still handling codes with complex They achieve enforcing an acyclic discipline amongst allow threads use queues fashion. This dissertation demonstrates that DSWPed only costs, but also effectively variable latency stalls better than single-threaded execution both in-order out-of-order issue processors comparable resources. It then performs thorough analysis of scalability automatically generated identifies conditions necessary peak performance. Next, shows even latencies well, frequency (once every 5 20 dynamic instructions) codes, makes sensitive intra-thread overhead imposed operations. In order understand issues surrounding undertakes methodical exploration design space support options PMT. Three new mechanisms varying cost-performance tradeoffs introduced shown perform 38% 200% state art.