Logical OR circuit for programmed logic arrays
作者： William T. Devine , William F. Washburn
DOI:
关键词: Internal resistance 、 Rise time 、 Output device 、 Voltage 、 Logical disjunction 、 Electrical engineering 、 Electronic engineering 、 Voltage source 、 Voltage drop 、 Dissipation 、 Engineering
摘要: An improved logical OR circuit is shown wherein the load resistance divided into drain and source resistance, each having a lower value than could be employed with single while at same time keeping power dissipation to low levels. The use of relatively resistances permits faster voltage rise time, thereby permitting programmed logic array (PLA) operation. drop across made small when output device conducting by providing substantially higher for respect input devices.
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