作者: Kenneth E. Rhodes
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摘要: A technique is disclosed for condensing the overall size of a PLA circuit and number elements involved in carrying out desired logical OR operation. This done by preconditioning product term AND array to be grounded source connected positive potential, polarities which are opposite those balance circuit. Therefore, if particular or search selected means its gate going positive, line output will rise potential instead falling. Since any element have this effect column elements, an function performed what otherwise PLA. The resultant localized change achieves significant reduction columns necessary carry conventional