Internal clock generator, system and method
作者： Chul-ho Lee , Jin-Yub Lee
DOI:
关键词: Synchronous circuit 、 Electronic engineering 、 CPU multiplier 、 Clock generator 、 Clock signal 、 Clock gating 、 Clock domain crossing 、 Clock skew 、 Digital clock manager 、 Computer science
摘要: An internal clock generator, system and method of generating the are disclosed. The comprises detecting level an operating voltage within system, comparing to a target corresponding detection signal, selecting between normal alternate having period longer than in relation signal on basis selection.
lens.org 参考文章(11)
Fabrizio Meli, Santi Carlo Adamo, Gaetano Di Stefano, Ugo Mari, Circuit to switch between clock signals and related method ,(2006)
Hiroshi Kiso, Semiconductor memory device and electronic information device using the same ,(2003)
Takashi Fujise, Step-down circuit, power supply circuit, and semiconductor integrated circuit ,(2003)
Teruhiko Saitou, Reset control circuit and reset control method ,(2005)
Takahiko Sato, 貴彦 佐藤, Semiconductor device and initial setting method for semiconductor device ,(2000)
Kyung Seung Jun, System clock frequency changing circuit for digital logic ,(2003)
Sanada Koji, SEMICONDUCTOR STATIC MEMORY ,(1992)
Lee Dong Yoon, Sim Dae Yoon, INNER CLOCK GENERATING CIRCUIT HAVING AN ANALOG PUMPING STRUCTURE ,(2000)
Na Won Gyun, Lee Si Yeol, Lee Jeong Bae, DOUBLE DATA RATE SYNCHRONOUS DRAM INTEGRATED CIRCUIT TESTED BY LOW SPEED TEST DEVICE ,(2000)