A Comparative Study of Placement of Processor on Silicon and Thermal Analysis

作者: C. Ramya Menon , Vinod Pangracious

DOI: 10.1007/978-3-642-27308-7_69

关键词: Computer scienceSiliconThermal analysisComputer hardwareIdleThermal management of electronic devices and systemsFloorplanIntegrated circuitThrough-silicon viaElectrical engineeringMulti-core processor

摘要: Today when we have stepped into the second decade of this century, integrated circuits are getting more and complex with multicore processors. With technology scaling, devices being a small area. As result, heat dissipation in (ICs) has increased. The processor is one highest generating components an IC. temperature generated circuit varies factors like number processors, modes, their dimensions arrangement on Silicon. In paper presenting two simulation results. First was obtained by analyzing how area occupied affects distribution. This study extremely important as processors scales down technology. to find out location modes can affect distribution at 2.4GHz frequency were analyzed both active idle modes. lowest temperatures hotspot each case analyzed.

参考文章(14)
Frank P. Incropera, Fundamentals of Heat and Mass Transfer ,(1985)
Mircea R. Stan, Kevin Skadron, Marco Barcella, Wei Huang, Karthik Sankaranarayanan, Sivakumar Velusamy, HotSpot: a Dynamic Compact Thermal Model at the Processor-Architecture Level Microelectronics Journal. ,vol. 34, pp. 1153- 1165 ,(2003) , 10.1016/S0026-2692(03)00206-4
Shamik Das, Anantha Chandrakasan, Rafael Reif, Design tools for 3-D integrated circuits asia and south pacific design automation conference. pp. 53- 56 ,(2003) , 10.1145/1119772.1119783
A. W. Topol, D. C. La Tulipe, L. Shi, D. J. Frank, K. Bernstein, S. E. Steen, A. Kumar, G. U. Singco, A. M. Young, K. W. Guarini, M. Ieong, Three-dimensional integrated circuits Ibm Journal of Research and Development. ,vol. 50, pp. 491- 506 ,(2006) , 10.1147/RD.504.0491
Jiérâi Vlach, Kishore Singhal, Computer Methods for Circuit Analysis and Design ,(1983)
J. Cong, Yan Zhang, Thermal via planning for 3-D ICs international conference on computer aided design. pp. 745- 752 ,(2005) , 10.5555/1129601.1129707
Shengqing Shi, Xi Zhang, Rong Luo, The thermal-aware floorplanning for 3D ICs using Carbon Nanotube asia pacific conference on circuits and systems. pp. 1155- 1158 ,(2010) , 10.1109/APCCAS.2010.5775003
Haihua Su, Frank Liu, Anirudh Devgan, Emrah Acar, Sani Nassif, Full chip leakage estimation considering power supply and temperature variations Proceedings of the 2003 international symposium on Low power electronics and design - ISLPED '03. pp. 78- 83 ,(2003) , 10.1145/871506.871529
Krste Asanović, Seongmoo Heo, Kenneth Barr, Reducing power density through activity migration Proceedings of the 2003 international symposium on Low power electronics and design - ISLPED '03. pp. 217- 222 ,(2003) , 10.1145/871506.871561
Ankur Jain, Robert E. Jones, Ritwik Chatterjee, Scott Pozder, Zhihong Huang, Thermal modeling and design of 3D integrated circuits intersociety conference on thermal and thermomechanical phenomena in electronic systems. pp. 1139- 1145 ,(2008) , 10.1109/ITHERM.2008.4544389