Three-dimensional integrated circuits

摘要: Three-dimensional (3D) integrated circuits (ICs), which contain multiple layers of active devices, have the potential to dramatically enhance chip performance, functionality, and device packing density. They also provide for microchip architecture may facilitate integration heterogeneous materials, signals. However, before these advantages can be realized, key technology challenges 3D ICs must addressed. More specifically, processes required build with devices compatible current state-of-the-art silicon processing technology. These show manufacturability, i.e., reliability, good yield, maturity, reasonable cost. To meet requirements, IBM has introduced a scheme building based on layer transfer functional circuits, many process design innovations been implemented. This paper reviews steps aspects that were developed at enable formation stacked layers. Details regarding an optimized are presented, including descriptions 1) glass substrate through-wafer alignment; 2) oxide fusion bonding wafer bow compensation methods improved alignment tolerance during bonding; 3) single-damascene patterning metallization method creation high-aspect-ratio (6:1 108 vias/cm2), extremely aggressive wafer-to-wafer (submicron) capability.