Test methodologies and design automation for IBM ASICs
作者： P. S. Gillis , T. S. Guzowski , B. L. Keller , R. H. Kerr
DOI: 10.1147/RD.404.0461
关键词: IBM 、 Engineering 、 Design for testing 、 Application-specific integrated circuit 、 Embedded system 、 Integrated circuit 、 Quality (business) 、 Set (abstract data type) 、 Electronic design automation 、 Test (assessment)
摘要: IBM manufactures a very large number of different application-specific integrated circuit (ASIC) chips each year. Although these are designed by many customers having various levels test experience and all tight deadlines, ASICs have reputation for their high quality. This quality is due in part to the heavy focus on design (DFT) use automation help ensure that customers' can be manufactured, tested, diagnosed with minimal engineering effort. Prospective ASIC technologies find an explicit set DFT methodologies follow which provide relatively painless, almost push-button approach generation high-quality, “sign-off” vectors chips. paper discusses used support enables designers so productive methodologies. Data given several recently processed chips, some outside IBM.
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