作者: J. A. Waicukauski , E. Lindbloom , E. B. Eichelberger , O. P. Forlenza
DOI: 10.1147/RD.332.0149
关键词:
摘要: A new method for generating weighted random patterns testing LSSD logic chips and modules is described. Advantages in using versus either deterministic or test are discussed. An algorithm calculating an initial set of input-weighting factors a procedure obtaining complete stuck-fault coverage presented.