作者: M. Ishiduki , J. Matsunami , A. Nitayama , R. Katsumata , H. Aochi
DOI:
关键词: Optoelectronics 、 Flash memory 、 Flash (photography) 、 Electronic engineering 、 Charge trap flash 、 Transistor 、 NAND gate 、 Multi-level cell 、 Chip 、 Logic gate 、 Engineering
摘要: We propose pipe-shaped bit cost scalable (P-BiCS) flash memory which consists of NAND strings folded like a u-shape instead the straight-shape. P-BiCS technology achieves highly reliable film program and erase (P/E) operation is managed by Fowler-Nordheim (FN) tunneling, that originated strong curvature effect its small pipe radius, low resistance source line layered metal wirings tightly controlled diffusion profile for select-gate (SG) transistor due to thermal budget. The effective 1-bit cell area 0.00082 mum2 functionality are successfully demonstrated using 32 Gbit test chip with 3-dimensionally 16 stacked layers multi-level-cell (MLC) 60 nm technology.