Low-voltage 32 Msample/s parallel pipelined switched-current ADC
作者： B.E. Jonsson , H. Tenhunen
DOI: 10.1049/EL:19981373
关键词: Switched current 、 Electrical engineering 、 Compensation (engineering) 、 Low voltage 、 Fin (extended surface) 、 Noise (electronics) 、 Spurious-free dynamic range 、 Communication channel 、 Electronic engineering 、 Computer science 、 Sampling (signal processing)
摘要: A parallel switched-current A/D converter is presented. Eight time-interleaved ADCs operating at 4 Msample/s are used to increase the sampling rate. With channel compensation, measured SFDR > 50 dB 32 with fin = 1.13 MHz. The performance of this experimental design limited by noise and a fixed-pattern timing error that not removed compensation algorithm.
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