A 70 MS/s 8-bit differential switched-current CMOS A/D converter using parallel interleaved pipelines
作者： M. Bracey , W. Redman-White , J.B. Hughes , J. Richardson
DOI: 10.1109/TENCON.1995.496358
关键词: A d converter 、 Pipeline transport 、 Electronic engineering 、 Computer science 、 Bandwidth (signal processing) 、 CMOS 、 Cmos process 、 Time interleaved 、 Switched current 、 8-bit
摘要: A 70 MS/s CMOS A/D converter is presented. Four double-sampling differential switched-current pipelines are used in a time interleaved structure to achieve high sampling rate. Particular issues addressed the matching of signal copies whilst maintaining full analogue bandwidth, and minimising corruption during propagation. The experimental fabricated standard 0.8 /spl mu/m 5 V digital process without special options.
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