New current-mode wave-pipelined architectures for high-speed analog-to-digital converters

摘要: In this paper, two new architectures for high-speed CMOS wave-pipelined current-mode A/D converters (WP-IADCs) are proposed and analyzed. the WP-IADC architectures, theory is applied to both pipeline structures, called full (FWP-IADC) indirect transfer (ITWP-IADC). FWP-IADC, each stage uses structure without switched-current cell circuits. ITWP-IADC, cells incorporated into stages which divided several sections with controlled clocks. Therefore, ITWP-IADC performs optimally in terms of speed accuracy WP-IADCs. Generally, WP-IADCs have advantages high speed, input frequency, efficiency timing usage, clock-period flexibility precision enhancement, reduced number overall data path linearity improvement. According theoretical analysis on minimum sampling clock period proportional intrinsic delay current mirror increased rise/fall time stage. The HSPICE simulation results reveal that, under Nyquist rate 8-b resolution, a 20 54 MHz can be achieved FWP-IADC two-section respectively. If four used, operated at 166 an frequency 8 MHz. To experimentally verify correct function architecture implemented by using 0.35-/spl mu/m technology. measurement successfully demonstrate feasibility IADC applications ADCs.