A 0.5-V 0.4–2.24-GHz Inductorless Phase-Locked Loop in a System-on-Chip
作者： Kuo-Hsing Cheng , Yu-Chang Tsai , Yu-Lung Lo , Jing-Shiuan Huang
DOI: 10.1109/TCSI.2010.2089559
关键词:
摘要: A phase-locked loop (PLL) is proposed for low-voltage applications. new charge pump (CP) circuit, using gate switches affords low leakage current and high speed operation. voltage-controlled oscillator (LV-VCO) composed of 4-stage delay cells a segmented mirror (LV-SCM) achieves gain (KVCO), wide tuning range, good linearity. LV-SCM generates more with small area by switching the body rather than gate. The PLL implemented in standard 90-nm CMOS regular VT (RVT) devices. Its output jitter 2.22 ps (rms), which less 0.5% period. phase noise - 87 dBc/Hz at 1-MHz offset from 2.24-GHz center frequency. Total power dissipation frequency, 0.5-V supply 2.08 mW (excluding buffers). core 0.074 mm2.
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