Fast-locking PLL based on a novel PFD-CP structure and reconfigurable loop filter
作者： Alireza Abolhasani , Morteza Mousazadeh , Abdollah Khoei
DOI: 10.1049/IET-CDS.2019.0561
关键词: Charge pump 、 CMOS 、 Phase frequency detector 、 Low-power electronics 、 Power (physics) 、 Electronic engineering 、 Phase-locked loop 、 Dead zone 、 Computer science 、 Electronic circuit
摘要: In this study, the design routine of a novel phase frequency detector and charge-pump (PFD-CP) is discussed. The main advantage proposed circuit its improved dead zone performance as circuits PFD-CP have been merged to reduce latency structure. To justify this, by means reconfigurable loop filter, fast-locking low-power phase-locked (PLL) has implemented which can operate at range 100 MHz–1.2 GHz while power consumption 2.53 mW 1.2 GHz operating frequency. whole PLL in 0.18 µm complementary metal–oxide–semiconductor technology with 1.8 V supply. post-layout simulation results are provided show conformity theoretical assumptions circuit-level implementations depict locking time 0.54 µs
sci-hub.st 参考文章(35)
J. Wallberg, D. Leipold, P.T. Balsara, R.B. Staszewski, Chih-Ming Hung, K. Maggio, All-digital phase-domain TX frequency synthesizer for Bluetooth radios in 0.13/spl mu/m CMOS international solid-state circuits conference. pp. 272- 527 ,(2004) , 10.1109/ISSCC.2004.1332699
W. Hu, L. Chunglen, X. Wang, Fast frequency acquisition phase-frequency detector with zero blind zone in PLL Electronics Letters. ,vol. 43, pp. 1018- 1020 ,(2007) , 10.1049/EL:20071984
Ja-Yol Lee, Mi-Jeong Park, Byung-Hun Min, Seongdo Kim, Mun-Yang Park, Hyun-Kyu Yu, A 4-GHz All Digital PLL With Low-Power TDC and Phase-Error Compensation IEEE Transactions on Circuits and Systems. ,vol. 59, pp. 1706- 1719 ,(2012) , 10.1109/TCSI.2012.2206500
Soh Lip-Kai, Mohd-Shahiman Sulaiman, Zubaida Yusoff, None, Fast-Lock Dual Charge Pump Analog DLL using Improved Phase Frequency Detector international symposium on vlsi design, automation and test. pp. 1- 5 ,(2007) , 10.1109/VDAT.2007.372761
ROBERT C. CHANG, LUNG-CHIH KUO, HOU-MING CHEN, A LOW-VOLTAGE LOW-POWER CMOS PHASE-LOCKED LOOP Journal of Circuits, Systems, and Computers. ,vol. 14, pp. 997- 1006 ,(2005) , 10.1142/S0218126605002738
Yi He, Xiaole Cui, Chung Len Lee, Dongmei Xue, An improved fast acquisition PFD with zero blind zone for the PLL application international conference on electron devices and solid-state circuits. pp. 1- 2 ,(2014) , 10.1109/EDSSC.2014.7061226
Sumer Can, Yilmaz E. Sahinkaya, Modeling and simulation of an analog charge-pump phase locked loop international conference on advances in system simulation. ,vol. 50, pp. 155- 160 ,(1988) , 10.1177/003754978805000405
M.-S. Hwang, J. Kim, D.-K. Jeong, Reduction of pump current mismatch in charge-pump PLL Electronics Letters. ,vol. 45, pp. 135- 136 ,(2009) , 10.1049/EL:20092727
R.B. Staszewski, J.L. Wallberg, S. Rezeq, Chih-Ming Hung, O.E. Eliezer, S.K. Vemulapalli, C. Fernando, K. Maggio, R. Staszewski, N. Barton, Meng-Chang Lee, P. Cruise, M. Entezari, K. Muhamma, D. Leipold, All-digital PLL and transmitter for mobile phones IEEE Journal of Solid-state Circuits. ,vol. 40, pp. 2469- 2482 ,(2005) , 10.1109/JSSC.2005.857417
Xiang Gao, Eric A. M. Klumperink, Mounir Bohsali, Bram Nauta, A Low Noise Sub-Sampling PLL in Which Divider Noise is Eliminated and PD/CP Noise is Not Multiplied by $N ^{2}$ IEEE Journal of Solid-state Circuits. ,vol. 44, pp. 3253- 3263 ,(2009) , 10.1109/JSSC.2009.2032723