作者: Yi He , Xiaole Cui , Chung Len Lee , Dongmei Xue
DOI: 10.1109/EDSSC.2014.7061226
关键词: Reset (computing) 、 CMOS 、 Pulse (signal processing) 、 Enhanced Data Rates for GSM Evolution 、 Control theory 、 Process (computing) 、 Computer science 、 Loop (topology) 、 Detector 、 Electronic engineering 、 Phase-locked loop
摘要: An improved fast acquisition phase-frequency detector (PFD) for Phase-Locked Loop (PLL) is presented. The proposed PFD completely eliminates the blind zone, which caused by missing input edge during reset pulse. It has a linear output range and saturated when phase error in [0, π] [π, 2π]. simulation results with SMIC 65nm CMOS technology file show that, comparing published works, nonlinear gain faster lock process, improves maximum operating frequency to as higher 1GHz.