作者: Kun-Seok Lee , Byeong-Ha Park , Han-il Lee , Min Jong Yoh
DOI: 10.1109/ESSCIRC.2003.1257188
关键词:
摘要: This paper introduces a new-type phase-frequency-detector (PFD) for charge pump phase-locked-loops (CPPLLs). As the PFD is configured to separate reset part and delay independently, input signal edge data, which arrive during an added remove dead-zone, are not lost do output wrong information, resulting in faster locking property. The experimental results of proposed show reduced frequency acquisition time by about 30% compared with conventional case 70MHz voltage-controlled-oscillator (VCO) hopping PCS mobile applications. designed simulated SPECTRE prototype, together synthesizer, has been fabricated 0.5/spl mu/m BiCMOS technology.