A power efficient phase frequency detector and low mismatch charge pump in on-chip clock generator

摘要: In this manuscript, we propose a robust on-chip clock generator circuit using power efficient phase frequency detector and low current mismatch dual adaptive regulated cascode charge pump in 180nm UMC MPW RF process. The proposed PFD uses only 20 transistors is free from dead zone. It consumes of 5.4μW for an input reference 50MHz can support maximum 2.5GHz at PLL output. limits the variation charging discharging currents to 0.09% its biasing value, which designed be 182.5μA, change control voltage 0.4V 1.2V. This reduces jitter less than 2ps output 2.3GHz. avoids operational amplifiers design, resulting lesser rea without any loss functionality.