A power efficient PFD-CP architecture for high speed clock and data recovery application
作者： Madhusudan Maiti , Suraj Kumar Saw , Vijay Nath , Alak Majumder
DOI: 10.1007/S00542-019-04458-4
关键词: Robustness (computer science) 、 Phase noise 、 Electronic engineering 、 Phase frequency detector 、 CMOS 、 Computer science 、 Gate count 、 Charge pump 、 Schematic 、 Skew
摘要: This paper explores a speed and power improved dead zone free, low gate count CMOS phase frequency detector with charge pump (PFD-CP) for clock data recovery application. Implemented in 90 nm technology, the proposed circuit configuration estimates layout area of 420.66 μm2 burns as small 172.10 μW when simulated 5 GHz at supply 1.2 V Cadence Virtuoso platform. With elimination reset path available conventional PFD, this architecture doesn’t only become blind but it also offers lower noise output − 142.46 dBc/Hz − 131.145 dBc/Hz respectively 1 MHz offset. We have studied performance metrics skew without different extreme corners schematic post to manifest variation awareness robustness circuit. The scalability arrangement is endorsed technology.
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