Reference voltage circuit
作者： Masuhide Ikeda
DOI:
关键词: Electrode 、 Voltage reference 、 PMOS logic 、 Threshold voltage 、 Voltage 、 Materials science 、 Impurity 、 Power (physics) 、 Transistor 、 Optoelectronics
摘要: A depletion type PMOS transistor Q 1 and an enhancement 2 are serially connected to each other between power supply lines . gate electrode of the is formed from polysilicon including a P-type impurity source thereof. N-type drain voltage corresponding difference threshold generated at mutually section both MOS transistors as reference voltage.
lens.org 参考文章(8)
Richard W. Hull, Leonard Teslenko, MOS Phase lock loop synchronization circuit ,(1982)
Shin-ichi Imai, Charge transfer device with booster circuit ,(1988)
Taizo Kinoshita, Minoru Nagata, Kiichi Yamashita, Hirotoshi Tanaka, Nobuo Kotera, Satoshi Tanaka, Threshold voltage fluctuation compensation circuit for FETS ,(1988)
Andrezej Peczalski, Temperature compensation for semiconductor logic gates ,(1986)
Tatsuya Yoshie, Shin-ichi Imai, Charge transfer device with reset voltage generating circuit ,(1988)
Masanao Hamaguchi, 正直 浜口, Semiconductor device for reference voltage ,(1996)
Wayne C. Parker, John W. May, Bus transceiver including compensation circuit for variations in electrical characteristics of components ,(1983)
Stewart S. Taylor, High-impedance FET circuit ,(1990)