Overview of low-power ULSI circuit techniques

摘要: This chapter contains sections titled: Minimizing Power Consumption in Digital CMOS Circuits Overview of Low-Power ULSI Circuit Techniques Multi-Level Pass-Transistor Logic for ULSIs High Performance, Energy Efficient Master-Slave Flip-Flop Dissipation the Clock System highly pipelined Power-Delay Characteristics Adders Delay Balanced Multipliers Low Power/Low Voltage DSP Core Minimization VLSI Using Transistor Sizing, Input Ordering, and Statistical Estimation Design Analysis a Programmable Architecture/Program Optimization A Review Adiabatic Computing 2ND Order Computation with 2N-2P 2N-2N2P Microprocessor Based on Resonant Clocked Integrated Single-Phase Power-Clock Supply: Experimental Results