Apparatus and method for reducing power consumption in a computer system

作者： David B. Townsley , Helder Ramalho , Michael D. Johnson , Wing-Hong Chow

DOI:

关键词: Control logic 、 Power (physics) 、 Shut down 、 Computer hardware 、 Embedded system 、 Engineering 、 Double fault 、 Signal 、 Power consumption 、 State (computer science) 、 Interrupt

摘要: A method and apparatus for reducing the power consumption of a processor in computer system where programming structure running on determines when is an inactive state to cause clocking signals supply be disabled processor. The again coupled clock response periodic interrupt signal, non-periodic or bus request from peripheral device. Thereafter, control logic reenters state, such that disables decouples returns state. extended offer ability shut down structures alternate masters subsystem controllers within same system.