Memory integrated circuit device having self reset circuit for precharging data buses based on the detection of their discharge levels

作者: Hiroshi Toyoshima , Daisuke Shimadu , Masahiko Nishiyama

DOI:

关键词: Reset (computing)Electronic engineeringElectrical engineeringEngineeringIntegrated circuitSignalPower consumptionSignal lines

摘要: The invention provides a semiconductor integrated circuit device having signal transmission path realizing high speed and low power consumption with simple configuration. has for transmitting by discharging one of first lines corresponding to complementary input signals in plurality precharged precharge circuit, self reset detecting the discharge level pair out operating at timing later than period discharging.

参考文章(4)
Louis L. Hsu, Rajiv J. Joshi, Jeremy K. Stephens, Daniel W. Storaska, Embedded DRAM system having wide data bandwidth and data transfer data protocol ,(2002)
Kwan-Weon Kim, Young-Jin Yoon, DDR SDRAM for stable read operation ,(2002)
Fujita Hideo, SEMICONDUCTOR STORAGE UNIT ,(1986)
Ichikawa Tsutomu, SEMICONDUCTOR MEMORY DEVICE ,(1993)