Embedded DRAM system having wide data bandwidth and data transfer data protocol
作者： Louis L. Hsu , Rajiv J. Joshi , Jeremy K. Stephens , Daniel W. Storaska
DOI:
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摘要: A self-timed data communication system for a wide width semiconductor memory having plurality of paths is provided. The includes central path including at least one junction circuit configured exchanging signals between the and path. respective circuitry controlling resetting preparation subsequent transfer through in accordance with receipt an input monitor signal indicating that has been transferred to circuit. further banks storing data, wherein corresponding bank connected paths. operation initiated from generating control after operation.
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