Multiprocessor system with multilevel caches

摘要: Atomic memory references in a multiprocessor data processing system 6 require the appearance of coherent system. Writes or attempted writes to 18 are monitored order correctly resolve hits against reservation state. Each processor 10 has two caches 20, 40 associated therewith, arranged level cache having an "inclusion" property wherein all entries within first required be maintained higher 20. The second filters operations on bus 8 and forwards any traffic that may involve stored cache. A flag 42, 46 is set each time valid pending. Thereafter, replacement entry results automatic deletion corresponding included then reset response occurrence either operation which affects address address, permitting atomic achieved without necessity distributing address.