Multiple level caches

摘要: A system and method is disclosed for a multiprocessor (MP) having multiple levels of cache storage shared memory. which comprises microprocessors (MPU). The MPUs, have on-chip L₁ caches, are interfaced with external L₂ caches. D₂ directories situated parallel to the caches shadow maintain data coherence among all main memory, while decreasing amount interference Reducing permits MPUs perform at higher speeds further coupling additional (MP).