Multilevel storage hierarchy with a variable address mode

摘要: The disclosure provides a data processing system which contains multi-level storage hierarchy, in the two highest hierarchy levels (e.g. Ll and L2) are private (not shared) to single CPU, order be close proximity each other CPU. Each cache has line length convenient respective cache. A common directory an L1 control array (L1CA) provided for CPU access both L2 caches. is addressed by requesting logical addresses, of either real/absolute address or virtual address, according whichever mode in. entry representation derived from that previously missed directory. request "hits" if its requested any L2). presence field (LPF) included aid determining hit L1CA information supplement corresponding entry; used during LRU castout, but not critical path hit. translation lookaside buffer (TLB) determine hits. TLB output only infrequent times misses directory, translated (i.e. absolute address) then synonym location same cache, main storage, another multiprocessor using synonym/cross-interrogate directories.