A case study of system synthesis with non-synthesizable components using extended VHDL
作者： J.D.S. Babcock , A. Dollas
DOI: 10.1109/IWRSP.1995.518587
关键词: Compiler correctness 、 Compiler 、 VHDL 、 Programming language 、 Systems design 、 Hardware description language 、 Logic synthesis 、 Formal methods 、 Computer science 、 Computer architecture
摘要: Extensions to VHDL have been defined in order produce a compiler that allows for system design with synthesizable and non-synthesizable multi-chip subsystems. The has completed this paper presents case study made evaluate the merits limitations of approach. Finally, brief discussion is error generation. Capability results from use formal methods definition language extensions.
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