Extended VHDL for the rapid prototyping of systems with synthesizable and nonsynthesizable subsystems
作者： J.D. Sterling Babcock , A. Dollas
DOI: 10.1109/IWRSP.1994.315900
关键词:
摘要: System design is typically done in VHDL to facilitate top-down and enable the mapping of a many implementations. Reusability subsystems date has largely been performed with libraries synthesizable subsystems. This paper presents recommended extensions allow designer interact nonsynthesizable while still designing VHDL. The extended code passed through precompiler that outputs two standard files: simulatable model system, where are replaced by signals external hardware. >
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