Dynamically selecting processor cores for overall power efficiency
作者： Keith Farkas , Parthasarathy Ranganathan , Norman P. Jouppi , Robert N. Mayo
DOI:
关键词: Performance metric 、 Electrical efficiency 、 Hardware compatibility list 、 Power (physics) 、 Application software 、 Embedded system 、 System requirements 、 Multi-core processor 、 Computer science 、 Transfer (computing)
摘要: A computer system for conserving operating power includes a number of hardware processor cores that differ amongst themselves in at least their respective requirements and processing capabilities. monitor gathers performance metric information from each the is specific to particular run application software then executing. workload transfer mechanism transfers executing second core search reduced power. delay connected subsequent if may be conserved by such delay.
lens.org 参考文章(4)
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R. Kumar, K. Farkas, N.P. Jouppi, P. Ranganathan, D.M. Tullsen, Processor Power Reduction Via Single-ISA Heterogeneous Multi-Core Architectures IEEE Computer Architecture Letters. ,vol. 2, pp. 2- 2 ,(2003) , 10.1109/L-CA.2003.6